1. The fetch and execution cycles are interleaved with the help of?
a) Modification in processor architecture
b) Clock
c) Special unit
d) Control unit

2. The periods of time when the unit is idle is called as?
a) Stalls
b) Bubbles
c) Hazards
d) Both a and b

3. The addressing mode, where you directly specify the operand value is ?
a) Immediate
b) Direct
c) Definite
d) Relative

4. The Input devices can send information to the processor?
a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases

5. ISP stands for?
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure

6. To reduce the memory access time we generally make use of?
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s

7. MFC stands for?
a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command

8. The addressing mode which makes use of in-direction pointers is?
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode

9. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy?
a) True
b) False

10. The pipelining process is also called as?
a) Superscalar operation
b) Assembly line operation
c) Von Neumann cycle
d) None of the mentioned